CPU Senior Floor Plan Engineer

Job Details:

Job Description

The Role and Impact Defines the physical dimensions of the CPU IP with consideration for overall product costs such as die size optimization, die per reticle/good die per wafer maximization, and right technology selection as it pertains to metal layers and reuse strategy across different SKUs in a product family. Performs integration of all dies in a package and completes the relevant checks before tape out. Creates and physical database for the IP. Collaborates with architects to optimize the placement of IPs for latency as well as die area/aspect ratio.

Creates specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies. Collaborates with the clock design and logic design teams to deliver the physical block level floorplans for APR. Collaborates with the power delivery team on tradeoffs for metal allocation for signal and power. Business group You will join Intel Corporation's team focused on CPU design and development, contributing to the creation of groundbreaking technologies that enable world-class computing solutions.

This group thrives on innovation, delivering high-performance designs that support Intel's mission to shape the future of technology through the creation of industry-leading products.

Key Responsibilities

In this role you will be responsible for all the aspects of Floorplan and pin placement activities. You will engage with Architecture, DFT and package to arrive at optimal chip planning early in the design cycle. You will work closely with physical design cluster leads to comprehend design challenges and arrive at optimal floorplan. You will play critical role in die size estimation and in evaluating Floorplan tools, methods and flows. Planning boundaries and pin densities to facilitate high confidence timing closure and routability.

With your broad understanding of physical design you will play a critical role in identifying and solving multitude design issues at partition/cluster and full chip. Expertise with multiple aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I-O planning and hard IP integration.

Qualifications

Minimum Qualifications - Bachelor's degree in a relevant field such as Electrical Engineering, Electronics Engineering, or equivalent education, with 3+ years of hands-on experience OR Master's degree in a relevant field with 2+ years of hands-on experience. - Proven expertise in using Floor planning, APR flows, Physical Design Verification Flows using Synopsys or Cadence tools. - Proficiency in hierarchical design approach, top-down design, budgeting, timing and physical convergence. - Strong knowledge of submicron process nodes and layout verification methodologies such as LVS and DRC. - Experience at handling IP/partition/block with multiple voltage and clock domains, ESD strategies, mixed signal block integration, and advanced package…

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