SoC Compute/Memory Subsystem Architect

Job Details:

Job Description

About the Role The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.

We are seeking a Senior SoC Compute & Memory Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms. This role is responsible for end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems. You will optimize system-level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments. What You’ll Do Key responsibilities will include but not limited to: Cache Hierarchy and Coherency Architecture 1.

Define and evolve multi-level cache hierarchy (private/shared caches, system-level cache). 2. Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non-coherent interactions). 3. Evaluate tradeoffs between latency, bandwidth, scalability, and coherence domain complexity. Memory Subsystem Architecture 1. Architect system memory subsystems including: -DDR / LPDDR interfaces. -Memory controllers and scheduling policies. -Bandwidth provisioning and scaling strategies. 2. Work with Performance architect in define memory access models for compute, network, and accelerator subsystems. 3.

Ensure optimal balance between latency-sensitive control workloads and bandwidth-intensive datapath workloads. IO Memory and Virtualization Architecture (SMMU/IOMMU) 1. Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads. 2. Architect features such as: -Multi-tenant isolation and security boundaries. -Shared vs isolated memory models. 3. Ensure efficient interaction between host, IPU/DPU compute, and offload engines. System-Level Integration (Compute Network Storage) 1. Architect integration between: -Compute subsystem. -Network subsystem (packet processing pipelines). -Storage and accelerator subsystems. 2.

Optimize data movement across subsystems to minimize copies, latency, and bandwidth overhead. 3. Drive system architecture decisions for balanced SoC performance. Power, Efficiency, and Scaling Strategy 1. Define compute and memory strategies for power efficiency and DVFS scalability. 2. Architect mechanisms for: -Memory bandwidth throttling / prioritization. -Per-subsystem scaling. 3. Optimize performance-per-watt at system level. Multi-Generation Architecture Roadmap 1. Lead long-term roadmap for compute and memory…

Read the full posting