Senior Verification Engineer

Job Details:

Job Description

The Role and Impact You will be part of a highly skilled, agile design/verification team developing cutting-edge hardware for the NIC, IPU and AI domains. As a senior IP Design Verification Engineer, you will play a crucial role in ensuring the functionality and reliability of complex designs. You will technically lead teams in developing verification plans, creating test benches, and building environments to thoroughly validate meaningful parts of the chip — complex IPs and subsystems.

Your work will directly contribute to identifying and resolving bugs in the pre-silicon environment using simulation and/or Formal Property Verification techniques, ensuring robust designs that meet high-performance standards. We are intentional, fast adopters of AI as a working tool. We bring modern AI assistants and automation into every part of the verification flow — planning, stimulus and checker development, coverage analysis, debug and more. Business group You will be joining Intel's Central Engineering Group (CEG), a global organization responsible for designing and verifying industry-leading IPs and architectures that power Intel's NIC, IPU and ASIC products.

The group produces innovative technologies and solutions for hyperscalers, cloud providers, networking, AI and other specialized workloads. As part of this dynamic team, you will contribute to Intel's commitment to advancing silicon and system innovation.

Key Responsibilities

Own verification planning and execution for key IP features across IP and subsystem integration points Build scalable verification environments and targeted test plans with reusable test benches, checkers, VIPs, and behavioral models Collaborate closely with architecture, design, and software teams from specification through bringup; contribute across role boundaries when needed to unblock progress and maintain execution quality Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows Mentor and develop verification engineers; establish verification best practices and raise team-level execution quality Comfortable using AI-assisted development tools as part of everyday workflow; track record of delivering reusable, configurable verification collateral Qualifications:

Minimum Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. 10+ years of experience in functional design verification of ASIC, SOC or FPGA designs with expertise in System Verilog, OVM/UVM, and debugging tools. Proficiency…

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