Job · Santa Clara, CA · Full time

USB IP Design Verification Engineer

Intel Retiree Medical Plan Trust · $67.5M budget · Since 1996

Provides health coverage for retired US employees and their dependents.

Before you apply

FY2024 · Form 990Independent: from IRS data, not the org
Budget
$53.5M
spent in FY2024
Fine: from the org's Form 990.
Pt I · Ln 18
Spent on programs
100%
of spending
Looks good: 100% of spending went to programs; 75% or more.
Pt IX · Ln 25 · col B
Surplus or deficit
+21%
of revenue, FY2024
Looks good: revenue was at least expenses in the latest filing.
Pt I · Ln 19
Cash reserves
112 mo
of spending, in cash and securities
Looks good: 111.7 months of spending in cash; 3 or more.
Pt X · Ln 1–2 · Pt I · Ln 18
Latest return
FY2024
latest Form 990
Looks good: the latest return is for FY2024, 2 tax years back; within 2 tax years.
IRS e-file
IRS status
501(c)(9)
tax-exempt since 1998
Looks good: listed by the IRS.
IRS BMF
Looks goodFineWorth a lookConcernTap a box for the reason.

About the role

The org's own posting, as written

Job Details:

Job Description

Passionate IP design Verification Engineer who is motivated to work on fast moving USB IP development across various Client products. The engineer will have an opportunity to define a robust and high-quality test coverage plan to validate new generations of USB IP and challenging new architectural features.

The responsibilities cover: - Scoping and development of validation test plans for new architectural features and next generations USB IP development. - Developing test contents, coverage points and assertion checks. - Developing testbench infrastructure (monitors, scoreboards/checks, BFMs, etc) to close on validation coverage. - Finding and implementing correct measure for failing tests. - Continue to strive for innovation in problem-solving to improve test coverage in efforts to minimize project execution time while increasing efficiency. - Understanding SoC/Subsystem validation environment, and providing IP validation support.

Qualifications

Required Qualifications - Bachelor's degree in Electrical and Electronics Engineering, Computer Engineering, or a related field. - 0-1 years of hands-on experience in RTL design verification with demonstrated skills gained through internships, academic projects, coursework, or hands-on training. - Familiarity with System Verilog for design verification. - Basic knowledge of Verilog or VHDL RTL design. - Strong analytical and debugging skills, and creative in problem solving. - Effective communication, collaboration, and initiative in diverse team environments. - Positive energy and motivation to learn and adapt to evolving IP technologies and environments.

Preferred Qualifications

Understanding of USB protocol fundamentals. - Exposure to OVM/UVM verification methodology. - Hands-on experience with AI coding assistants (GitHub Copilot, ChatGPT, or similar). - Ability to critically evaluate AI-generated outputs for correctness. If you're passionate about driving innovation in high-speed IO technologies and eager to contribute to Intel's next-generation advancements, we encourage you to apply and join our team.

Job Type: College Grad Shift: Shift 1 (Malaysia) Primary Location: Malaysia, Penang Additional Locations: Malaysia, Kulim Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *…

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About Intel Retiree Medical Plan Trust

From its Form 990

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